Electrostatic Discharge (ESD) presents a special problem for semiconductor devices and particularly for metal oxide semiconductor (MOS) types of structures. The high voltage transient signal from a static discharge can bias an object with more than 10,000 volts and several amps of peak current. The unique hazard in MOS devices is the high electric field that can develop across a relatively thin gate dielectric used in the normal course of operation of the device. The gate dielectric, which is often oxide, can rupture under high electric field conditions, when the charge built up on the gate ruptures the gate oxide which normally acts as an insulator. The effects of the permanent damage caused by the rupture may not be immediately apparent; therefore, the possibility of gate oxide rupture constitutes a realistic reliability concern.
Common power MOSFETs have no protection against ESD or other excessive voltage signals applied to the gate. Silicon dioxide (SiO2) is often used as the gate dielectric in MOS devices. Typically, the rupture voltage for SiO2 can be as high as 10,000,000 Volts per centimeter. Modern MOS devices may have operational gate oxide of 400 Angstroms thickness. Therefore, the realistic rupture voltage for such a device is only about 40 V. One of the primary causes of ESD is contact with the human body during product assembly or maintenance. The “human body model” for ESD conditions typically involves a resistor in series with a capacitor. In the human body model (HBM), the effective body capacitance is charged to several thousand volts through even the simplest interaction with the environment. It is this charge that must be dissipated in the device. Thus, the human body appears to the power device as a high voltage battery during an ESD event.
Because ESD conditions are common in many working environments, many commercial MOS devices are equipped with self-contained ESD protection systems. These can be discrete or integrated with the main functional circuitry.
One method for protecting the gate of the devices from voltage above the oxide breakdown employs back-to-back diodes constructed in the polysilicon gate and then connected between the gate, source and/or drain terminals. This method is effective in improving the ESD rating of the MOSFET gate, and for avoiding over voltage damage. However, gate-source leakage current increases significantly since diodes constructed in polysilicon have much greater leakage current than in monocrystalline silicon. Maximum gate leakage current typically increases from 100 nanoamps to 10 microamps using this method. Some manufacturers have constructed other components in conjunction with the polysilicon diodes thus adding some limited control functions such as over current protection.
An example of a typical ESD protection structure commonly implemented on a CMOS IC is the circuit of FIG. 1a. There zener diodes 10.1 and 10.2 protect the gate of the N-mos power transistor 20 from very high voltages. Each zener diode pair is configured to point in opposite directions so that for current to flow in either direction across the pair, one zener breakdown voltage (plus one forward-biased diode drop) must be incurred. The reverse breakdown voltage in a zener diode is dependent upon the characteristics of the diode, but is typically much higher (on the order of several volts to tens of volts) than the forward-biased diode (on the order of 0.6 to 0.8 Volts). For extremely high voltages, the diode pair may conduct until the input voltage reaches a sufficiently low voltage so as to cause the pair to turn off. The zener diodes are fabricated such that they their reverse breakdown voltage plus one forward-biased diode drop is less than the rupture voltage for power transistor 20.
However, the use of polysilicon to produce a diode suitable for ESD protection circuitry has the disadvantages that the diodes are leaky, and thus a substantial leakage current may result. Others have proposed multiple polysilicon diode stacks with current limiting resistors between the stacks. See, for example U.S. Pat. No. 6,172,383. However, such proposals still have unacceptable leakage current. What the art needs is a protection circuit with limited or controlled leakage for normal operating conditions and ESD or high voltage protection for extraordinary conditions.